Self
Test - Chapter One
CIS343
(1-4) List the four basic
machine elements:
1.
2.
3.
4.
(5-6) What are the two main
categories of processor registers?
5.
6.
7-8. The
first of these is further subdivided into _____ registers and _____ registers.
Identify these special
purpose registers:
9. The
register containing the address of the next instruction to be executed is the .
. .
10. The
register containing the instruction being executed is the . . .
11. A
register or set of registers containing information about a process.
(12-15) List the four basic
processor actions:
12.
13.
14.
15.
(16-19) List four classes of
interrupts:
16.
17.
18.
19.
20. Diagram
the instruction cycle with interrupts.
(21-29) Complete the
description of the 9 steps of interrupt
processing.
21. A
device issues _____ to the processor.
22. The
processor _____ execution of the current instruction.
23. The
processor _____. If there is one, it
sends _____ to the device.
24. The
processor pushes the _____ and the _____ onto the _____.
25. The
processor loads the address of _____ into the PC.
26. The
interrupt handler saves information critical to the _____, such as the contents
of the _____.
27. The
_____ is processed.
28. The
saved _____ are retrieved and restored.
29. The
_____ and the _____ are restored.
Execution of the program resumes.
30. Two
approaches are taken to dealing with multiple interrupts. If we _____ while an interrupt is being
processed any incoming interrupts are handled in _____ order.
31. But
this does not take into account _____ or _____ needs.
32. Or
we could allow _____ interrupts to interrupt an _____.
(33-35) List 3 key
characteristics of memory.
33.
34.
35.
(36-38) Complete these
statements of key relationships among characteristics of memory.
36. Faster
access time, _____.
37. Greater
capacity, _____.
38. Greater
capacity, _____.
(39-42) As one goes down the
memory hierarchy, one encounters . . .
39. _____
cost per bit.
40. _____
capacity.
41. _____
access time.
42. _____
frequency of access of memory by the processor
(43-45) List the 3 stages of
the memory hierarchy.
43.
44.
45.
46. _____
is the key to the organization of memory.
47. The
hit ratio is the fraction of all memory accesses that are found . . .
48. Principle
of Data Organization: It is possible to organize data across the memory
hierarchy such that the percentage of accesses to each successively lower level
is _____ than that of the level above.”
49. The
motivation for cache memory: there
is a persistent mismatch between _____ and main memory _____.
50. The
solution: exploit the _____.
The goals of two level
organization of memory:
51. Performance
goal: have overall memory speed approach that of _____.
52. Cost
goal: have _____ of combined memory be close to that of the slower, cheaper
memory.
(53-55) Identify these I/O
communication techniques:
53. Processor
is involved only at beginning and end of data transfer.
54. I/O
module sets bits in status register to indicate task completion.
55. I/O
module interrupts processor upon task completion.
56. For
a high hit ratio, average memory access time is closer to the access time of
the _____ memory.
57. To
meet the cost goal of the two level memory organization, since the faster
memory is much more expensive than the slower, . . .
58. To
satisfy the performance goal we need a hit ratio of _____ or _____.
59. Numerous
studies have shown that with strong locality, a _____ of fast memory yields a
high hit ratio.
59. Conclusion:
the average cost per bit of two levels of memory will approach that of the
_____.
Word
Bank - Chapter 1 Self Test
CIS343
Answers to questions 1-29, except 20.
A. an
acknowledgment
B. address
registers
C. a
command
D. completes
E. Control
and Status Registers
F. data
processing
G. data
registers
H. data
transfer::processor-I/O module
I. data
transfer::processor-memory II. system
train
J. execution
control JJ. system
control stack
K. hardware
failure KK. tests
for an interrupt
L. ignores
the interrupt LL. timer
M. Instruction
Register (IR) MM. user-invisible registers
N. interrupt NN. the user program
O. the
interrupt handler OO. user-visible Registers
P. an
interrupt signal
Q. I/O
S. I/O
modules
T. lost
program values
U. main
memory
V. operating
system
W. OS
kernel
X. RAM
Y. registers
Z. register
values
AA. running
program
BB. processor
CC. Program
DD. Program
Counter (PC)
EE. Program
Status Word (PSW)
FF. software
GG. suspends
HH. system
bus
Answers to questions 30-59, except 58.
A. access
time(s) AA. Interrupt-Driven I/O
B. advertised
specials BB. large amount
C. average access time CC. more expensive memory
D. average
cost per bit DD. interrupt handler
E. capacity EE. in the faster memory
F. cheaper
lower-level memory FF. in the slower memory
G. cost GG. inverse
H. cost per
bit HH. less expensive
I. decreasing II. memory
speed
J. decreasing
cost per bit JJ. more
K. decreasing
frequency of access KK. more expensive
L. Direct
Memory Access LL. principle
of locality
M. disable
interrupts MM. processor
N. discard
interrupts NN. processor speed
O. disk OO. Programmed I/O
P. executing
program PP. off-line storage
Q. faster QQ. on the hit list
R. faster
access time RR. on-line
storage
S. fast
memory SS. outboard memory
T. higher
priority TT. RAM
U. increasing UU. relative
priority
V. increasing
cost per bit VV. reverse
W. increasing
frequency of access WW. sequential
X. lower
priority XX. slower
Y. greater
cost per bit YY. slower access time
Z. inboard
memory ZZ. slower memory
A1. small amount
A2. smaller
cost per bit
A3. speeds
A4. substantially
less
A5. time-critical
A6. user
generated
A7. cost of
the faster must be less than the cost of the slower
A8. size of
faster must be much smaller than size of slower memory
A9. size of
slower must be less than the size of the faster memory
B1. speed of
the slower must be greater than the speed of the faster memory