Chapter One Outline

CIS343

 

Basic machine elements

    Processor

    Main memory

    I/O modules

    System bus

 

Processor Registers

    User-Visible Registers

        data registers

        address registers

            Examples of special purpose address registers

                index register

                segment pointer

                stack pointer

    Control and Status Registers

        Program Counter (PC)

        Instruction Register (IR)

        Program Status Word (PSW)

            - a register or set of registers, includes condition codes

 

Instruction Execution

    Instruction Fetch and Execution

    Basic Instruction Cycle - Figure 1.2

    Basic Processor Actions

        Data transfer::processor-memory

        Data transfer::processor-I/O module

        Data processing

        Execution Control

    I/O Function

 

Interrupts

    Classes of Interrupts

        Program

        Timer

        I/O

        Hardware Failure

    Interrupts and the Instruction Cycle

        interrupt request

        Transfer of control via Interrupts - Fig. 1.6

        interrupt cycle

        Instruction Cycle with Interrupts - Fig. 1.7

        interrupt handler

    Interrupt Processing

        Changes in Memory and Registers for an Interrupt - Fig. 1.11

    Multiple Interrupts

        disabling interrupts

        define interrupt priorities

    Multiprogramming (Chapter 2)

 

The Memory Hierarchy

    3 key characteristics of memory

        cost

        capacity

        access time

    Key relationships

        faster access time, greater cost per bit

        greater capacity, smaller cost per bit

        greater capacity, slower access time

    Memory hierarchy - Fig. 1.14  :: as one goes down

         decreasing cost per bit

        increasing capacity

        increasing access time

        decreasing frequency of access of memory by processor

    Memory hierarchy - Fig. 1.14  :: 3 stages

        Inboard memory

            Registers

            Cache

            Main memory

        Outboard memory

            Magnetic disk

            CD-ROM

            CD-RW

            DVD + RW

            DVD-RAM

        Off-line storage

            Magnetic tape

            MO

            WORM

    Decreasing frequency of access is key to this organization of memory

        Note: ms = microsecond = 1 x 10^-6 second

        Note: word = “In programming, the natural data size of a computer.

            The size of a word varies from one computer to another, depending

            on the CPU.  For computers with a 16-bit CPU, a word is 16 bits (2

            bytes).  On large mainframes, a word can be as long as 64 bits.”

                (From Webopedia)

    Hit ratio (H) - “fraction of all memory accesses that are found in the

                faster memory.” (Stallings)

        Hit - accessed word is found in faster memory

        Miss - accessed word is not found in faster memory

    Principle - Locality of Reference (Denning)

        See Process Characteristics for more on locality

    Principle of Data Organization (Stallings)

        “It is possible to organize data across the memory hierarchy such that

        the percentage of accesses to each successively lower level is 

        substantially less than that of the level above.”

        - can be applied across more than two levels of memory

 

Cache Memory

    Motivation

        rate of instruction execution is limited by memory cycle time

        there is a persistent mismatch between processor and main memory

            speeds

        solution: exploit principle of locality

    Cache Principles

        Goals: have memory speed approach fast memory

                  provide large mem size at price of less expensive memory

    Cache Design

 

I/O Communication Techniques

    Programmed I/O

        I/O module sets bits in status register to indicate task completion

        Processor interrogates status of I/O module

    Interrupt-Driven I/O

        I/O module interrupts processor upon task completion

        Processor executes data transfer

    Direct Memory Access

        Processor is involved only at beginning and end of data transfer

 

Performance Characteristics of Two-Level Memories

    Locality

        Program execution is basically sequential

        Program references tend to be localized to a few procedures

        Most iterative constructs are short

        Data structure storage often is localized

    Spatial locality: referenced memory locations are clustered

    Temporal locality: tendency is to access memory locations recently used

    Operation of Two-Level Memory

        Fig. 1.15 => for high value of H, average access time is closer to the

            access time of the faster memory

    Performance

        Goal: Want average cost per bit of combined memory to be close to the

            cost of the slower, cheaper memory

        Since faster is much more expensive than slower, size of faster must be

            much smaller than size of slower memory (Fig. 1.22)

        Fig. 1.23 => need hit ratio in range of 0.8 or 0.9 to satisfy performance

            goal

        Key ingredient - degree of locality

        Fig. 1.24 & numerous studies show - with strong locality small amount

            of fast memory yields high hit ratio

        Conclusion: average cost per bit of two levels of memory will approach

            that of the cheaper lower-level memory