CIS343                 Chapter One Review

 

Identify these basic elements of a computer system:

1. Stores data and programs

2. Structures and mechanisms that provide for communication among processors, main memory and I/O modules.

3. Controls the operation of the computer and performs its data processing functions.

4. Move data between the computer and its external environment.

 

Identify these processor registers used in the data exchange process.

5. Used for exchange of data between I/O module and processor.

6. Contains data to be written into memory and receives data from memory.

7. Specifies the address in memory for the next read or write.

8. I/O address register to specify a particular I/O device.

 

9. T/F: A processor includes a set of registers that provide a level of memory that is faster and larger than main memory.

 

10-11. What are the two main classes of processor registers?

 

Identify these user-visible registers.

12. Contain main memory addresses of data and instructions.

13. Dedicated register that points to the top of the stack.

14. Can be assigned to a variety of functions by the programmer.

15. Contains an index into main memory, calculated from a base address.

16. Holds the address of the starting location of a segment.

 

Identify these control and status registers(or parts thereof).

17. Contains the most recently fetched instruction.

18. Holds the address of the instruction to be fetched next.

19. Contains status information.

20. Bits set by the processor or hardware as the result of operations.

 

 

21. T/F: “If the processor designer has a functional understanding of the operating system to be used, then the register organization can to some extent be tailored to the operating system.”  This quote from our text demonstrates the ongoing interaction between the design of hardware and of software.

22. The basic function performed by a computer is _____.

23. The program to be executed consists of _____.

24. Draw the diagram of the Fetch-Execute cycle.

 

Identify these categories of action taken by the processor.

25. Transfer of data from processor to memory or from memory to processor.

26. Specify that the sequence of execution be altered.

27. Transfer of data - processor to or from peripheral device.

28. Perform arithmetic or logical operation.

 

Answer these questions regarding Figure 1.4.  (Assume that the panels are numbered from 1 to 6, starting at the upper left corner and going left to right.

29. In step #1, why was the value 1940 placed into IR?

30. In step#2, why does the value 0003 appear in AC?

31. Does the hypothetical machine whose operation is shown in Figure 1.4 increment the PC before or after instruction execution?

32. In step #4, why does the value 0005 appear in AC?

 

33. T/F: A DMA operation can proceed while the processor is busy performing other operations.

34. T/F: Interrupts are provided primarily to improve processing efficiency, since most external devices are much faster than the processor.

 

Identify these classes of interrupts.

35. Generated by a failure such as a power failure or a memory parity error.

36. Generated by some condition that occurs as a result of program execution.

37. Generated by an I/O controller.

38. Allows operating system to perform certain functions on a regular basis.

 

39. T/F: With interrupts, the processor can be engaged in executing other instructions while an I/O operation is in progress.

 

40. When an external device becomes ready to be serviced, the I/O module for that device _____ to the processor.

41. The OS program that determines the nature of the interrupt and performs the actions needed is called the _____.

42. T/F: Overhead costs are incurred with the process of using interrupts to handle I/O devices and other peripherals.

43. T/F: During an interrupt the value of the PC is not changed, so as to not lose the place at which instructions of the user programmer are being executed.

 

44. Draw the Instruction Cycle diagram for a system employing interrupts.

 

45. Before control can be transferred to the interrupt handler the processor must save information needed to _____.

46. The minimun information required is found in the _____ and the _____ registers.

47. How is control passed to the interrupt handler?

48. Do the contents of user-visible registers ever need to be saved by the interrupt handler?

 

Answer these questions regarding Figure 1.11.

49. In Figure 1.11(a), why is the value Y placed into the PC?

50. In Figure 1.11(b), why is the value N+1 found on the Control Stack?

51. In Figure 1.11(a), why is the value T - M placed into the Stack Pointer?

 

52. What are the two approaches that can be taken for dealing with multiple interrupts?

53. What is the drawback to disabling interrupts?

 

54. In the design of computer memory, there is a tradeoff between three key characteristics of memory.  These are:

55. Across the spectrum of technologies, state the relationships that hold:

          between access time & cost:

56. . . . between capacity & cost:

57. . . . between capacity & access time:

58. A typical resolution to the dilemma this causes the designer is to employ a memory hierarchy.  As one goes down the hierarchy, tell what occurs:

          to cost:

59. to capacity:

60. to access time:

 

61. What requirement with respect to this hierarchy must be met in order to achieve the goals of this design?

62. The basis for the expectation that this requirement will be realized is the principle of _____.

 

With respect to Figure 1.15,

63. What is the average access time when H=0?  Why?

64. What is the average access time when H=1?  Why?

 

65. On all instruction cycles, the processor accesses memory at least once, to _____, and often one or more additional times to _____ and/or to _____.

66. Therefore, the rate at which the processor can execute instructions is limited by _____.

67. This causes a significant problem because of _____.

68. Since it has not been possible to have memory cycle times match processor cycle times, what solution has been provided?

69. In cache memory, what is the purpose of the tag?

 

Identify these issues in design of cache memory.

70. How large should cache be?

71. How much data should be transferred from main memory to cache?

72. Which cache location should a new block occupy?

73. When a new block is placed into cache, which block should be overwritten?

74. When should memory be updated to reflect changed contents of cache?

 

Appendix 1A:

75. Which two-level memory system has an access time ratio of 5 to 1?

76. 1,00 to 1?

77. Which system is implemented by special hardware?

78. . . . hardware/software combination?

79. . . . system software?

80. Which might have a block size of 4 to 128 bytes?

81. . . . 64 to 4096 bytes?

82. Which gives the processor direct access to second level memory?

83. Which gives only indirect access?

84. T/F: Studies have shown that a typical program spends a high percentage of time in sequential execution.

85. Studies have shown that in C and Pascal programs a window depth of 8 will need to shift only 1% of the time.  What does that have to do with locality of reference?

86. _____ locality refers to the tendency of program execution to involve a number of memory locations that are clustered.

87. _____ locality refers to the tendency for a processor to access memory locations that have been used recently.

88. If memory location m is accessed at time t, it is likely to be accessed at time t+k, where k has a very small value.  This would be a more precise statement of the principle of _____.

89. If memory location m is accessed at time t, then it is likely that soon thereafter memory location m+k will also be accessed. This would be a more precise statement of the principle of _____.

90. _____ locality reflects the tendency of a processor to access instructions sequentially.

91. Execution of an iteration loop would be an example of causality for _____.

92. The tendency of a program to access data locations sequentially is an example of causality for _____.

93. In formula 1.1, why is (T1 + T2) multiplied by (1 - H)?

94. What is the maximum possible value of Ts?

95. What is the minimum possible value of Ts?

96. In formula 1.2, why is the denominator S1 + S2?

97. Why is the numerator C1S1 + C2S2?

98. Figure 1.22 shows that if C1 >> C2, then we need to have _____.

99. According to Figure 1.22, which yields a lower relative combined cost:  when C1/C2 = 100 & S2/S1 = 10 or when C1/C2 = 1000 & S2/S1 = 500?

100. What principle does this illustrate?

101. According to Figure 1.22, which yields a lower relative combined cost:  when C1/C2 = 10 & S2/S1 = 10 or when C1/C2 = 1000 & S2/S1 = 1000?

102. What principle does this illustrate?

103. If we desire Ts to be approximately equal to T1, what condition must be met?

104. What ratio is referred to as access efficiency?

105. According to Figure 1.23, what is the access efficiency of virtual memory when the hit ratio is 0?  Why?

106. According to Figure 1.23, what hit ratio is needed for a disk cache system in order to achieve an access efficiency of 0.01?

107. Why, in Figure 1.23, if T1 = T2 is the access efficiency 1 only if the hit ratio is also 1 (since access to M2 is no slower than access to M1)?

108. With strong locality what relative size of M1 to M2 is needed to achieve a hit ratio of 0.8?

109. . . . with moderate locality?

110. What do we conclude from that?

111. If S1/S2 = 0.4, what degree of locality is needed to achieve an access efficiency of 0.4 for a cache memory system?